1. Field of the Invention
The present invention relates to a method of fabricating a low-power CMOS device. Although the present invention is suitable for a wide scope of applications, it is particularly suitable for forming a shallow trench on a silicon substrate using a gate mask and negative photoresist to enable an extremely low profile for a junction after completion of lightly doped drain and source/drain implantations.
2. Discussion of the Related Art
A fabricating process of a low-power CMOS device includes depositing a gate oxide layer and polysilicon on a substrate, depositing a gate sidewall spacer layer over the substrate including the gate oxide layer and polysilicon by low-pressure chemical vapor deposition, forming a gate structure by active ion etch, performing lightly doped drain and source/drain implantations, forming a self-aligned silicide for metallization, depositing a silicon nitride (SiN) layer having a thickness of 70-100 nm by plasma deposition, and forming an interlayer dielectric and M1 contact hole. The SiN layer is deposited as a buffer layer for transistor protection over the substrate. A low-power CMOS device fabrication method according to a related art is illustrated in FIGS. 1A-1C.
FIGS. 1A and 1B show a gate pattern after deposition of a gate oxide layer 3 and a gate-doped polysilicon 4 formed 210-230 nm thick. The gate oxide layer 3, the gate-doped polysilicon layer 4, a tetra-ethyl-ortho-silicate layer 5, and a silicon nitride layer 6 are stacked on a substrate 1. A lightly doped drain (LDD) layer 2 is formed between the substrate 1 and the tetra-ethyl-ortho-silicate layer 5 by implantation.
FIG. 1B also shows a gate structure formed by reactive ion etching. A gate sidewall 5a and a spacer 6a are formed. A barrier layer 8 is formed by low-pressure chemical vapor deposition. As shown, the implantation depth of a source/drain layer 11 beneath the LDD 2 is substantial.
FIG. 1C shows an interlayer dielectric 15 and an M1 contact hole 12 after forming the LDD 2 and the source/drain layer 11 by implantation. A self-aligned silicide for metallization and a 70-100 nm thick SiN layer 8 formed by plasma deposition are shown. The SiN layer 8 is a buffer layer for transistor protection.
The considerable depth of the source/drain junction, however, causes short-channel effects and junction leakage current.